A 2x Time-Interleaved 24-GS/s 12-Bit Resistive DAC
This study evaluates a 12-bit Time-Interleaved (TI) Digital-to-Analog Converter (DAC) operating at 24 GS/s, incorporating Return-to-Zero (RZ) scheming within its sub-DAC cores. Initially, the TI DAC demonstrates superior performance compared to a traditional single-channel DAC. However, the evaluation in this thesis reveals that the TI DAC is more sensitive to timing errors, such as clock skew and