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A 50-MS/s two-step flash-ΔΣ time-to-digital converter (TDC) using a 2-channel time-interleaved time-domain register with an implicit adder/subtractor demonstrates a 3rd order noise-shaping. The TDC is fabricated in 40-nm CMOS and consumes 1.2 mA from a 1.1 V supply. At frequencies below 1.25 MHz, the TDC error integrates to 103 fsrms, which is equal to an equivalent resolution of 1.6 ps.
