Low Power Unrolled CORDIC Architectures
This paper shows a novel methodology to improve unrolled CORDIC architectures. The methodology is based on removing adder stages starting from the first stage. As an example, a 19-stage CORDIC is used but the methodology is applicable on CORDICs with an arbitrary number of stages. The CORDIC is implemented, simulated, and synthesized into hardware. In the paper, the performance is shown to be incr
