Case study on Universal Verification Methodology(UVM) SystemC testbench for RTL verification
This Master’s thesis aims to conduct a case study on using Universal Verification Methodology (UVM) in SystemC for Register-Transfer Level (RTL) verification. Verification of ASICs is very important nowadays especially in terms of production costs, time to market and the sustainability of products. As Moore’s Law is in motion, verification gets large, complex, and time-consuming. Re-usability and
