Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip
The increasingamount of test data needed to test SOC (System-on-Chip) entailsefficient design of the TAM (test access mechanism), which is usedto transport test data inside the chip. Having a powerful TAM willshorten the test time, but it costs large silicon area to implementit. Hence, it is important to have an efficient TAM with minimalrequired hardware overhead. We propose a technique that make
