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On Batch recipe Structures Using High-Level Grafchart

Batch processes are very common and important in e.g. the chemical industries. The international standard ISA88.01 defines the terminology, the functionality and the models for batch control systems. The production specification of how to produce a batch, is called a recipe. This paper shows how high-Level Grafchart, a Grafcet and High-Level Petri net based programming language can be used to repr

Scattering from a frequency selective surface supported by a bianisotropic substrate

In this paper a method for the analysis of a frequency selective surface (FSS) supported by a bianisotropic substrate is presented. The frequency selective structure is a thin metallic pattern — the actual FSS — on a plane supporting substrate. Integral representations of the fields in combination with the method of moments carried out in the spatial Fourier domain are shown to be a fruitful way of

Test Scheduling for 3D Stacked ICs under Power Constraints

This paper addresses Test Application Time (TAT) reduction for core-based 3D Stacked ICs (SICs). Applying traditional test scheduling methods used for non-stacked chip testing where the same test schedule is applied both at wafer test and at final test to SICs, leads to unnecessarily high TAT. This is because the final test of 3D-SICs includes the testing of all the stacked chips. A key challenge