Gate Layout and Process Reliability Co-Optimization in High-Speed Vertical III–V Nanowire Metal-Oxide-Semiconductor Field-Effect Transistor Technology
High-speed vertical III–V nanowire transistors utilize their channel material for high frequency and low noise performance. A device layout revision to optimize gate resistance, in a trade-off to gate-source capacitance, is presented. A two-step redesign of the established device layout is proposed. First step is demonstrated with fabricated structures. The second step predicts the design transiti
