III-V heterojunction nanowire tunnel FETs monolithically integrated on silicon
In this presentation we will discuss our recent progress on the integration of InAs/Si p-tunnel FETs (TFETs) and InAs/GaSb n-TFETs on SOI wafers. Local III-V growth is enabled by the development of Template-Assisted Selective Epitaxy (TASE) [1-4]. Both polarity devices have scaled geometries with cross-sections on the order of 30nm. The p-channel InAs/Si TFETs are developed based on our previously